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Havent played in over two years so this was a good opportunity to get back into it! Short solo on my Roland TD6, recording is done with the GoPro HD so really the sound is not that good.
Short Drums Solo for the Xilinx Sales Conference 2012 - Rock the World		 Videojuego retro implementado sobre una FPGA Xilinx Spartan3E para la asignatura LSDP2.
Harcanoide		 Some Facts about PLICProgrammable logic integrated circuits, or as they are often called PLICs, are mysterious devices, and few are aware of them. Although their appearance is absolutely common -- a standard chip. Recently, however, the subject of FLIC has become quite popular, because in fact, this technology makes it possible to make ones own chip with its own architecture.FLICs are large matrix type integrated circuits, allowing to implement logic functions of great complexity in a programmatic way. A sequential execution of commands is the physical limitation of performance inherent in all traditional processor architectures. All sorts of tricks, such as superscalarity, multiple assembly lines, multiple cores, do not really brighten the picture.FLIC architecture has potentially greater performance rate compared with microcontrollers and DSP processors, and this is due to the possibility of hardware parallelism of calculations.Still, the trend of FLIC development is not in competition with microprocessors.The modern approach to the design of complex systems is rather a successful combination of architectures of PLICs and processors. Thus, there is an organic supplement: possibility of high-speed data processing in real-time implementation of highly specialized algorithms with critical timing diagrams; a large number of user outputs with a wide range of processors to solve mathematical and algorithmic problems.Another application to build high-speed PLICs is building <b>...</b>
Some Facts about PLIC		 Xilinx is the worlds leading provider of All Programmable technologies and devices, beyond hardware to software, digital to analog, and single to multiple die in 3D ICs. These industry leading devices are coupled with a next-generation design environment and IP to serve a broad range of customer needs, from programmable logic to programmable systems integration.
Xilinx Inc. Overview
Dont want the background music? go here: www.youtube.com Aerial video of Xilinx Ireland (Citywest Business Campus near Dublin) for the Xilinx Sales Conference 2012 Photo Competition. Equipment: - SkySurfer RC plane - Turnigy 9x TX - GoPro HD
2012 Xilinx WorldWide Conference - Rock the World		 Aerial video of Xilinx Ireland (Citywest Business Campus) for the Sales Conference Photo Competition. Equipment: - SkySurfer RC plane - Turnigy 9x TX - GoPro HD
2012 Xilinx Worldwide Sales Conference - Rock the World		 WARNING FOR EDUCATIONAL PURPOSE ONLY!!! ONCE AGAIN FOR EDUCATIONAL PURPOSE ONLY!!! Xilinx ISE Design Suite v12.4 The ISE
Xilinx ISE Design Suite v12.4 Free Download with serial !		 Soldering fixed the problem! Chip Info (courtesy Gradius2 over at forum.videohelp.com) Main CPU: XILINX SPARTAN XC3S1200E CIRRUS (Stereo Input/Output Audio): CS4265 ADV7393 BCPZ-3 (Composite, S-Video, Video Component & RGB): ANALOG DEVICES (HDMI/DVI Transmitter or Output, 10-bit DACs): AD9889B BSTZ-165 ANALOG DEVICES (HDMI/DVI Receiver or Input and Component, 12-bit ADCs): ADV7604 BBCZ-5P Please take a second to hit that THUMBS UP button if you like my videos and Subscribe for great justice!
Blackmagic Intensity Shuttle Disassembly and PCB chip info
Review of Basys2 Xilinx FPGA Board
Basys2 Xilinx FPGA Dev.Board Review		 This Application show an LabVIEW VI that is working as a driver for a 7-segment display. project weblink: decibel.ni.com code weblink: decibel.ni.com Requirements: Application Software: LabVIEW Professional Development System 8.5 Addon Software: LabVIEW FPGA Module 8.5 I developed this Application on my Xilinx SPARTAN3E Starter Board. I used a Kingbright SA52-11 7-segment display. Enjoy www.mobile-it.be Vincent Claes
7-segment Display with LabVIEW FPGA on a Xilinx SPARTAN3E Starter Board		 B
18.Mai V		 Hello friends, This is a automation robot project, this project has configured in Xilinx FPGA (spartan 3an) and vhdl coding has been used to program that system, This robot simply follow a black path, and when any obstacle encountered in front of robot then robo will stop until the obstacle has been removed. This project having one more feature that this robo will only run when it see any reflecting surface, means if you take it in your hand then it will not work, This feature gives a strength to the robot that if the robot is running on any height from the earth surface like boundary-less roof, table etc, then the robo will automatically stop at the end of boundary. and the robo will not fell down to ground. I hope you like this video, for more details about the project, or if you have any query then please contact me at nsdobal@gmail.com Thank you for watching
FPGA Project : Path Follower with obstacle detector Robot.mp4
Este video tutorial muestra la forma de crear un proyecto de esquem
Crear Proyecto Esquem		 Este video tutorial muestra la forma de simular un dise
Simalaci		 Este video tutorial muestra la forma de crear un proyecto de VHDL en Xilinx ISE 13.1 para una FPGA Spartan3N.
Crear Proyecto VHDL en Xilinx		 LED instalado numa Xilinx XC2C64A CPLD Core Board Pirata. Video dedicado ao Cacildo Poncio eo Leorod199 (Outerspace Brasil).
Xilinx XC2C64A Pirata - Xbox 360 Slim Reset Glitch - LED
FPGA XOR Gate
Xilinx FPGA XOR Gate		 SAN JOSE -- Innovation comes in all forms. Just ask SAFE -- or the Security Administration For Earthquakes -- the five-member Miller Middle School and Kennedy Middle School squad that competed Saturday in the record-making 25th Annual The Tech Challenge. Students were charged with creating a device to pluck a survivor from an earthquake-ravaged bridge. SAFE cobbled together a solution made of magnets and PVC half-inch pipes, an Altoid container, and a sock, said team member Aditya Kotak, 14. And while their ingenuity didnt garner the top prize of the day (the team did win 2nd Place for Best Engineering Design Journal), it was representative of the myriad ways more than 1400 students from around the Bay Area creatively went about solving this years The Tech Challenge: Shake Rattle and Rescue. The Tech Challenge, presented by Cisco as part of a three-year sponsorship comprising financial resources, employee volunteers and a technology donation, introduces and reinforces the scientific and engineering process with a hands-on team project. Through the competition, students acquire key skills for a 21st-century global society. The competitions focus on a real-world problem distinguishes it from many other science-based programs for youth in grades 5 through 12. Today we saw the future of Silicon Valley, and the future is bright, said Tim Ritchie, president of The Tech Museum. A signature program of The Tech Museum, The Tech Challenge celebrates its 25th year and has <b>...</b>
The Tech Challenge 2012 Highlights		 In this demo CPLD XC2C256-7 is programed to generate one of the basic demo effects: Rotozoomer. TFT it as usually 640x480x18-bit TFT Sharp LQ064V3DG01. Implementing sine/cosine lookups is a bit complicatated task for CPLD so it has only 32-steps per halfwave (rest is interpolated). Because of this its not 100% smooth but if it rotates fast enough its not visible. :)
XILINX CoolRunner 2 + TFT = Rotozoomer		 Quick demo of my 4-bit multiplier coded in VHDL.
4-bit multiplier on Xilinx Spartan-3 FPGA
The first video of the pitch section of my (mostly) digital Theremin At this point it is more of a proof of concept, and is nowhere near a finished product. The movie starts out with me pressing the calibrate button which zeros out the DPLL. I then demonstrate the basic inherent linearity by playing rough octaves via open and closed hand movements at various distances. The pitch is somewhat cramped near the antenna and the abrupt drop at the low end could have been made more linear had my body been positioned closer. The linearity is so good that Im going to leave it alone for now and move my development efforts on to other sections, such as voicing and left hand control. The pitch section here is producing a raw square wave for now. There is a tuner section that you can see operating across the bottom that shows which note is currently playing. It needs more LEDs than this demo board has, it will likely have 24 (2 per note: 1 for on pitch and 1 for between notes, making a total of one octave displayed, I may also implement octave indicators) once I start fleshing out the prototype. Except for a very simple analog front end (AFE) its all implemented in a Xilinx Spartan 3 FPGA and coded in verilog. More to come I hope. Join me over at Theremin World where the design is described in more detail, and for links to the code and simulation: www.thereminworld.com
Digital_Theremin_2012-05-13_01.avi		 FPGA implemented template matching algorithm track selected object by calculating min error of local/global matching. Algorithm saves new template if matching error arrives predefined threshold. It is albe to choose the coefficients of matching filter to decrease the influence of border elements on total error. The object trajectory is drawing on monitor in real-time. The frame with object marker and path can be optionaly send to PC. Program works on 25MHz only with 60fps and VGA resolution camera. Xilinx array xc4vsx35 and Aptina grayscale camera is used for this implementation. Project is created in VHDL.
FPGA-based object tracking using adaptive template matching		 Pierwsze starcia z uk
FPGA + HD44780		 This is a video showing the successful interfacing of PS/2 keyboard (Keybord to host and host to keyboard) written in VHDL and simulated in Xilinx Spartan-3e Starter kit FPGA board. As you can see, when I change the switch position, the LEDs of the keyboard light as a command XED has been sent to the keyboard and after that X07. This tells the keyboard to switch on the LEDs (here all LEDs switched on as we sent X07). You can see also that when I push down any button on the keyboard, the LEDs of the board lit. The LEDs shows the Scancode of each button on the keyboard. For instance if I push down the button Q (for AZERTY keyboard) A (for QWERTY keyboard) we get 00011100. Normally after releasing the button a break code is sent, to follow the previous example we will have XF0 X1C. but I just filtered the XF0 so its not shown in the video. The code written will be uploaded soon in google code after I included this module to the Plasma CPU If you have any questions about this, Ill be happy to try to answer them Dont forget to subscribe and comment.
VHDL PS/2 Keyboard in Xilinx Spartan-3e FPGA (Demo)
XILINX CoolRunner 2 CPLD XC2C256 drives 18-bit parallel 640x480 TFT module Sharp LQ064V3DG01. In this demo Ive tried to fit small bitmaps into CPLD. The image has some 800 pixels and almost all CPLD terms have been used for it. Pixel clock runs at some 25MHz, frame rate at 60Hz or so. Since the display has high contrast its quite complicated to take a picture or capture some video so the quality is not well. More info: www.elektronika.kvalitne.cz
XILINX CoolRunner 2 + 640x480x18-bit TFT		 Xilinx is making it easier to bring world events home with end-to-end broadcast design platforms that drive down cost and power, while increasing the ability to differentiate and upgrade on the fly.
Xilinx End-to-End Broadcast Platforms		 Xilinx Kintex-7 FPGA Display Targeted Reference Designs enable display designers to develop 4K2K displays ahead of the competition -- without the need for new equipment or 4K2K content. Targeted Reference Designs:
Kintex-7 FPGA Display Targeted Reference Designs (Japanese w/ Subtitles)		 Demonstration of a single-chip, full spectrum (160 channel), CCAP-compliant design platform utilizing Xilinx 28nm 7 series FPGAs.
Xilinx EdgeQAM Targeted Design Platform
A demonstration of my (sped-up) digital clock for my EGCP 441 class. User can change minutes and hours with the two push buttons, as well as reset the clock to 12:00 with the leftmost push button. This was coded in VHDL in Xilinx Project Navigator.
Digital Clock on Xilinx Spartan-3 FPGA Board		 Xilinx Spartan-6
Implementaci
I-TRIS implementado en una FPGA		 In the present an autonomous mobile robot was developed that is capable to explore an indoor environment (with a smooth floor), and recognize litter (placed on the floor) with homogeneous color with the help of an on-board camera. The recognition is based on the color of the litter. The color calibration regarding the litter-color is necessary before the application. The area exploration is based on a simple raster-pattern algorithm. The robot is capable to sense walls with an IR sensor. The litter removal part of by he robot is presently developed and tested. The central controlling unit of the robot is a Xilinx Spartan 3e FPGA board with an IP core developed by Xilinx ISE in VHDL language.
Litter collecting robot with FPGA based shape recognition to Digilent Contest
This video talks about the requirements for Xilinx Zynq 7000 Extensible Processing Platform. After reviewing the requirements, we discuss the Maxim designed power architecture used on the ZedBoard development platform, a platform designed by Avnet and Digilent around the Zynq 7000 EPP.
Xilinx Zynq 7000 EPP Powered by Maxim: Power Video #2		 This video talks about the requirements for Xilinx 7 series devices. After reviewing the requirements, we dive into the Maxim designed power module that was created to support the Avnet Mini Module Plus development platform.
Xilinx 7 Series Powered by Maxim: Power Video #1		 Analog Devices takes you inside the Boston event to witness the exciting activity taking place at these events worldwide. Hear how ADI, the analog signal processing experts, is enabling advanced technology solutions for Xilinx FPGAs. Explore our solutions for Xilinx FPGAs: www.analog.com
Experience the action at X-fest 2012 with Analog Devices		 DOWNLOAD: letitbit.net letitbit.net letitbit.net letitbit.net letitbit.net letitbit.net letitbit.net Xilinx ISE Design Suite 12.4 All Platforms x86/x64 | 6.8GB A program package for Xilinx ISE Design Suite v12.4 is designed for the implementation of digital systems on FPGA company Xilinx. ISE WebPACK (Free) ISE Design Suite (All Editions) ChipScope Pro and ChipScope Pro Serial IO Toolkit PlanAhead Design and Analysis System Generator for DSP Platform Studio and Embedded Development Kit (EDK) Software Development Kit (SDK) Lab Tools: Standalone Installation Extras. Information: Distribution is represented by two archives *. tar with the permission of the moderator gellmara. Completely identical to official archives, so if anyone downloaded on xilinx.com, then join the hand. Version: 12.4 Build M.81d.2.0 Developer: Xilinx Web Developer: www.xilinx.com Bit depth: 32bit +64 bit Compatibility with Vista: complete Compatible with Windows 7 full time Language: English Medicine: Present System Requirements: Microsoft Windows XP Professional (32 and 64 bit) Microsoft Windows Vista Business (32 and 64 bit) Windows 7 Red Hat Enterprise Linux 4 WS-32bit Red Hat Enterprise Linux 4 WS-64bit Red Hat Enterprise Linux 5 WS-32bit Red Hat Enterprise Linux 5 WS-64bit Suse Linux Enterprise 11 32-bit Suse Linux Enterprise 11 64-bit
DOWNLOAD FREE Xilinx ISE Design Suite 12.4 All Platforms x86x64 FULL


































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